In general, a frequency divider used in a wireless communication system is used in a frequency synthesizer. A frequency synthesizer is used to fix a local oscillation frequency, output from a voltage-controlled oscillator (VCO), at a selected channel frequency. A frequency divider may be designed in a current mode logic (CML) configuration that is high in operation speed and low in power consumption.
FIG. 1 is a circuit diagram of a conventional frequency divider designed in a CML configuration.
Referring to FIG. 1, a CML-based frequency divider 10 includes four stages 30, 31, 32 and 33. The first and third stages 30 and 32 are differential amplifiers that use a gate voltage as an input signal, and the second and fourth stages 31 and 33 are D-latches that are connected in a master-slave configuration. The operations of the first and fourth stages 30 and 33 and the second and third stages 31 and 32 may be determined according to two clocks CK and CKB with opposite phases, and output voltages OUT and OUTB are output accordingly.
According to the above configuration, the swings of the output voltages OUT and OUTB are determined by a bias current Ib and a load resistance RL. Since the output voltages OUT and OUTB are designed to have a very small value in comparison with a power supply voltage VDD, and a transistor performs a switching operation at high speed, this configuration may be advantageous in a high-speed operation. Also, the configuration may maintain the operation speed and the power consumption at the optimal values by controlling the bias current Ib.
Where a conventional CML-based frequency divider is fabricated through a deep submicron CMOS process with a gate length of 130 nm or less, MOS transistors may be stacked in a three-layer configuration.
However, since a power supply voltage may be lowered to about 1 V in a deep submicron process with a gate length of 130 nm or less, it is difficult to supply a sufficient power supply voltage for biasing all of MOS transistors of three-layer configuration in a saturation region. Thus, this design may be unsuitable for aa frequency divider that operates at high speed at a low voltage.